Formal Verification of the VAMP Floating Point Unit
نویسندگان
چکیده
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
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عنوان ژورنال:
- Formal Methods in System Design
دوره 26 شماره
صفحات -
تاریخ انتشار 2001